The methods and systems herein relate to providing foundry customers with Integrated Circuit (IC) graphic design data files for photomask plotting that allow for full place, route & checking capability of proprietary Intellectual Property (IP), while the IP developer cloaks the internal structure of the IP when viewed by the customer, typically an IC designer. This cloaking allows IC designers to use the IP developer's proprietary IP within their chip designs, while protecting the developer's IP from reverse-engineering by the customer, or others who have access to the IC data. This cloaking may be achieved by generating non-proprietary modified graphic data file(s) and netlist file(s) for the proprietary IP. These modified files are provided to ‘non-trusted’ IC design teams, instead of the original proprietary files. The modified files enable the IC design teams to complete all the necessary IC design and checking activities, using standard IC design software and design techniques—without requiring encryption or other non-standard design software or techniques. The final IC design may be then released to a ‘trusted’ IC fabrication facility, where the non-proprietary graphic data file(s) are replaced with the original proprietary file(s), prior to the fabrication process.
IC graphic data files, i.e., commonly used GDSII or OASIS data files, are used in the design of ICs and give complete IP design information to customers by IP developers, and are therefore not advantageous in their unmodified state to be given to customers. Once the customers have added their designs to the IC graphic data files, the IC graphic data files are given to IC foundries for final IC fabrication.
Objects contained in an IC graphic data file are grouped by assigning numeric and/or hierarchical attributes to them including a “layer number,” “datatype” or “texttype”. These graphic data files encapsulate hierarchical layout data for interchange between computer design systems, mask writing tools and mask inspection/mask repair tools.
Generally, the data within an IC's graphic data files may be organized hierarchically by cell with, in some instances, lower-level references to other dependent cells. Ideally, all cell layout data may be based on foundry-verified process data. A cell can be a simple (NAND gate, OR gate, XOR gate, etc.) logic circuit or it can comprise as much as the entire functionality for an embedded microprocessor. The content of the cell may be arbitrarily defined according to its anticipated use when connected with other cells during logic design. Mostly, a library file contains layer-by-layer transistor-level geometric (polygons) and non-geometric data that represents how, at the cell level, the cell should be manufactured.
A finished logic design shows how a set of cells chosen from a cell library for a particular design are to be connected. Chip-level layout design uses a netlist from logic design to place cell-level library files from the same library, (and/or multiple other sources), used in logic design and then add the routing that connects the placed cells together as one integrated circuit. After chip-level optimizations are made, the final output may be a single design data file containing optimized but still raw placement, routing and cell layer data for the entire integrated circuit.
Typically, the raw design layout data still requires finishing so that the layout, when transformed from data to shaped flashing beams of light and electrons actually print onto a mask or wafer as intended. Once finished, the modified layout of the chip may be fractured from a polygon-based representation to a geometrically equivalent representation of the data using smaller (machine-printable) geometric shapes. The fractured data may be stored separately as a fractured design data file.
Mask data preparation (MDP) is the step that translates an intended set of polygons on an integrated circuit layout into a form that can be physically written by the photomask writer. Usually this involves fracturing complex polygons into simpler shapes, often rectangles and trapezoids that can be written by the mask writing hardware. Typically a design may be delivered to mask data preparation in GDSII or OASIS format, and after fracturing is written out in a proprietary format specific to the mask writer.